1. Field of the Invention
The present invention relates in general to a method of fabricating shallow trench isolation (STI), and more specifically relates to a method of fabricating shallow trench isolation by using SiN.sub.x as a liner layer.
2. Description of Related Art
The device isolation structures are used to prevent the carriers from flowing between the adjacent devices through the substrate. The device isolation structures are formed between the adjacent field effect transistors (FETs) in dense semiconductor circuits, such as dynamic random access memories (DRAMs), to reduce charge leakage produced by FET. The most conventional and common technology for forming a field oxide region is the local oxidation of silicon (LOCOS). Due to the growth of the LOCOS technology, this technology has provided effective device isolation with an acceptable level of reliability. However, there are several drawbacks in LOCOS technology, especially the problems produced from the bird's beak. In a small device, the LOCOS field oxide structure cannot provide effective isolation. So, in high-density devices, it is replaced by shallow trench isolation that can be easily scalable.
The shallow trench isolation is a technology that a trench is formed in the substrate by using the anisotropic etching method. The trench is then filled with oxide to form the device field isolation structure. Because of the advantage of being able to scale and avoiding the drawbacks of bird's beak encroachment of the conventional LOCOS technology, shallow trench isolation is an ideal isolation technology for high integrated devices.
FIGS. 1A through 1C are schematic, cross-sectional views showing the process for forming shallow trench isolation according to a conventional method.
Referring to FIG. 1A, a pad oxide 102 is formed on the substrate 100 by using the thermal oxidation. Then a silicon nitride layer 104 is formed on the pad oxide layer 102 by using low-pressure chemical vapor deposition (LPCVD). The silicon nitride layer 104 is patterned. The silicon nitride layer 104, the pad oxide layer 102 and the substrate 100 are etched anisotropically to form a trench 106 on the substrate 100.
Referring to FIG. 1B, a liner oxide layer 108 is formed on the substrate 100 surface in the trench by thermal oxidation. An oxide layer 110 is formed over the mask layer 104 by atmospheric pressure chemical vapor deposition (APCVD) or high density plasma chemical vapor deposition (HDPCVD) and filling the trench 106 with oxide material. The densification step is proceeded to the oxide layer 110 under the high temperature of about 1000.degree. C.
Referring to FIG. 1C, parts of the oxide layer 110 are removed by chemical mechanical polishing (CMP) by using the mask layer 104 as a polishing stop layer. The mask layer 104 and the pad oxide layer 102 are removed sequentially to form a plug 100a in the trench 106.
Whatever the oxide layer 110 is formed by APCVD or HDPCVD, the ions produced by chemical reactions or the charges produced by plasma are trapped by the liner oxide layer 108. This induces the remaining of static electricity. On the other hand, the non-bonided oxygen molecules in the reaction penetrate and diffuse into the active region of the substrate 100. This effects the conductivity of the devices.
In the U.S. Pat. No. 5,747,866, Ho et al. describe forming a silicon nitride layer over the liner oxide layer in order to prevent the above drawbacks. The formation of the silicon nitride layer includes that a silicon nitride layer is deposited and then put the substrate into the furnace to produce a high temperature anneal. However, the formation of the silicon nitride layer by furnace has the stress problem. The stress may cause the defects of the single crystal semiconductor substrate easily.